A typical driver circuit for driving a capacitive load is shown in FIG. 1. The driver circuit comprises a pre-driver circuit, N-channel and P-channel drive transistors and an off-chip capacitive load. The pre-driver circuit supplies the enable signals ENN and ENP for the N-channel and P-channel drive transistors, respectively. An inductance on the output pin, which couples to the capacitive load, is an inherent feature of this arrangement and may extend to 15 nH for low cost packages.
On fast transitions of the input signal and hence the output signal, particularly when the output pin goes from a high logic state (VDD) to a low logic state (GND), the ground pin GND is required to supply a current spike to discharge the capacitive load, as shown in FIG. 3. However, due to the inductance on the output pin, the signal on the ground pin GND follows the enable signal ENN of the N-channel drive transistor. The spike then decays and oscillates, due to the LC circuit formed by the load capacitor and the pin inductance, with a typical period of, ##EQU1## Where L is the inherent inductance on the input pin and C.sub.load is the capacitance of the load.
The oscillations may be greater than the voltage level Vol which represents the amplitude of the maximum voltage recognized as a logic `0`, or `1` depending on the logic convention implemented. This causes a greater delay in the completion of the transition from the high logic state to the low logic state. In some cases, an oscillation which exceeds Vol can be detected as a double transition by the `driven` circuit, thereby producing incorrect results and errors.
A few methods have been developed to address the problems described above. One method, known as gradual switching, involves splitting the driver circuit into sections, such that each section turns on, one after the other. Such a method avoids the generation of spikes, but slows down the transition of the output signal.
Another technique involves adding resistances in the charge/discharge path of the driver circuits. In most cases, the resistance is added in the output path of the driver circuit. In some cases, it is done in the enable path or the supply path. However, this technique also slows down the transition.
Thus, the known methods provide a solution at the expense of transition speed. It is therefore desirable to provide a circuit which addresses the problems described above without compromising the transition speed.